module extin_ctrl
			(
			 clock, resetn,
			 rst, sig,
			 sig_sel,
			 dac_out
			);

input			clock, resetn;
input			sig_sel;

input	[13:0]	rst;
input	[13:0]	sig;

output	[13:0]	dac_out;

reg		[13:0]	dac_out;

always @(posedge clock or negedge resetn)
	begin
		if(!resetn)			dac_out <= 0;
		else if(!sig_sel)	dac_out <= rst;
		else				dac_out	<= sig;
	end

endmodule
